Integrated circuit and laminated leadframe package

ABSTRACT

A method of making a semiconductor device ( 100 ), comprising attaching a top surface of a first laminate ( 630 ) to a bottom surface of a second laminate ( 650 ) to form a leadframe ( 620 ) and mounting a semiconductor die ( 102 ) to the leadframe to form the semiconductor device.

BACKGROUND OF THE INVENTION

[0001] The present invention relates in general to semiconductor devicesand, more particularly, to small footprint packaged integrated circuits.

[0002] Electronic system manufacturers continue to demand componentswith higher performance and reliability along with a reduced physicalsize and manufacturing cost. In response, semiconductor manufacturersare developing techniques to reduce the component size and cost bymounting multiple components on a single leadframe that is encapsulatedto form a single integrated circuit package.

[0003] The size of an integrated circuit package is determined in partby the minimum feature size of the package's leadframe, which sets thewidth and spacing of the leads. The minimum feature size typically isabout equal to the thickness of the leadframe metal, which is a functionof the mechanical requirements of the package and the electrical andthermal specifications of the encapsulated circuit. For example, highpower circuits often require thicker leadframe metal to support highcurrent levels and adequately dissipate heat generated by the circuit.Furthermore, the width and spacing of the leads needed to handle theincreasing power, thermal dissipation, and speed requirements placefurther restrictions on reducing the size of an integrated circuitpackage.

[0004] Small interconnect feature sizes previously have been achieved bymounting the circuitry on an interposer. An interposer is a type ofprinted circuit board with layers of thin metal foil sandwiched betweendielectric layers and etched to produce the interconnect lines thatelectrically connect to the components mounted on the interposer. Themetal foil is thin, so small feature sizes are achievable. However, forhigh current devices, the interposer's thin metal lines must be madewide, which offsets the benefit of using a thin foil layer and increasesthe package footprint. For high power applications, the high thermalresistance of the interposer's thin metal foil results in inadequateheat removal. Moreover, interposers have a high fabrication cost, whichfurther limits their application.

[0005] Other devices such as power transistors often require multipleleads in order to provide sufficient current carrying capacity. Suchmultiple leads also function as a means for providing a thermalconduction path to carry heat away from the die. Such multiple leads areinefficient, introduce excessive costs, and increased defectopportunities.

[0006] Power transistors and other devices are also packaged in ballgrid array (BGA) packages. Power transistors in BGA packages have thesource connection made on the bottom of the die, that is the side of thepackage facing the customer printed circuit board. Thus heat conductedaway from the die by the source connection is undesirably propagated tothe customer printed circuit board. It would be an advantage in manydevices to propagate the heat away from the printed circuit board.Furthermore, BGA packaged devices require additional processing steps toform bumps on the semiconductor die bonding regions, which is expensive.

[0007] Hence, there is a need for a semiconductor device and packagethat can house multiple components in a small footprint, has a highcurrent and thermal dissipation capability and a high reliability whilemaintaining a low manufacturing cost.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is an exploded isometric view of a group of integratedcircuits at a selected stage of fabrication;

[0009]FIG. 2 is a cross-sectional view of a packaged integrated circuit;

[0010]FIG. 3 is a cross-sectional view of the packaged integratedcircuit in an alternate embodiment;

[0011]FIG. 4 is an isometric view of the integrated circuit in anotheralternate embodiment,

[0012]FIG. 5 is an isometric view of the integrated circuit in anotheralternate embodiment,

[0013]FIG. 6 is an exploded isometric view of the integrated circuit inyet another alternate embodiment, and

[0014]FIG. 7 is a schematic showing the electrical equivalent of theintegrated circuit of FIG. 6.

DETAILED DESCRIPTION OF THE DRAWINGS

[0015] In the figures, elements having the same reference number havesimilar functionality.

[0016]FIG. 1 is an exploded isometric view of an integrated circuitarray 10 at a selected stage of fabrication including a leadframe matrixcomprising a laminate matrix 2, a laminate matrix 4 and an overmold orblanket encapsulant 8. A plurality of component sets 6 is mounted topredetermined locations of laminate matrix 2. A singulated device fromarray 10 is referred to as an integrated circuit 100 that is shown priorto singulation. Array 10 is shown as being formed with two laminatematrices but, in some applications, it is advantageous to form leadframeuse three or more laminate matrices to achieve a desired level offunctionality. Note that component sets 6 are shown as individualcomponents in order to simplify the description, but often includemultiple electrical components mounted using a standard pick-and-placetool or similar equipment.

[0017] Laminate matrix 2 is formed from a sheet of rolled copper orother conductive material which is patterned to form an array ofsimilarly configured leadframe laminates 20 for mounting component sets6. Laminate matrix 2 is patterned by etching, stamping, milling oralmost any other standard leadframe patterning process. Laminate matrix2 includes alignment holes 11 through which alignment posts (not shown)are inserted for alignment during fabrication. Laminate matrix 2typically has a thickness greater than about fifty micrometers.

[0018] Laminate matrix 4 is formed in a similar fashion as laminatematrix 2 from a sheet of rolled copper or other conductive materialwhich is patterned to form an array of similarly configured leadframelaminates 40 whose patterns typically are different from the pattern ofleadframe laminates 20. A plurality of alignment holes 13 is positionedon the alignment posts mentioned above to align laminate matrices 2 and4 so that leadframe laminates 40 overlie their corresponding leadframelaminates 20. Laminate matrix 4 typically has a thickness greater thanabout fifty micrometers and need not be of the same thickness ormaterial as laminate matrix 2. For example, in one embodiment, laminatematrix 2 has a thickness of about fifty micrometers to facilitateetching features with small dimensions, e.g., a high lead density, whilelaminate matrix 4 has a thickness of one thousand micrometers toselectively provide a high thermal or electrical conductivity.

[0019] Array 10 is fabricated as follows. A top surface 5 of laminatematrix 2 is coated with a film of low temperature solder, a conductiveepoxy or other conductive material that has both conductive and adhesiveproperties and can be processed at temperatures less than about threehundred degrees Celsius. A bottom surface 3 of laminate matrix 4typically is coated with the same material.

[0020] Component sets 6 are then mounted to their specified locationsand alignment holes 11 and 13 are used to align laminate matrices 2 and4 while bottom surface 3 is brought into contact with top surface 5.Laminate matrices 2 and 4 then are disposed in a hot press or otherstandard solder reflow tool to mechanically bond bottom surface 3 to topsurface 5, thereby also forming an electrical connection betweenlaminate matrices 2 and 4. Depending on the application, and if notperformed earlier in the fabrication cycle, other fabrication processessuch as wire bonding typically are performed after laminates 2 and 4 arestacked and attached.

[0021] After laminate matrices 2 and 4 are attached, the assembly isplaced in a molding tool and encapsulated using a standard thermoset orthermoplastic molding compound to form blanket encapsulant 8. Blanketencapsulant 8 covers component sets 6 and exposed surfaces of laminatematrices 2 and 4 that are within an encapsulant region 9 on a surface 22of laminate matrix 4. The encapsulation process leaves a bottom surface7 of laminate matrix 2 uncovered or exposed in order to provide leadsfor making external electrical connections to integrated circuit 100after singulation.

[0022] After blanket encapsulant 8 is cured, laminate matrices 2 and 4and blanket encapsulant 8 are sawn along predetermined cut lines tosingulate individual packaged integrated circuits. For example, cutlines 14, 24, 16 and 26 define the path of a saw blade that singulatesintegrated circuit 100 from array 10 to produce an individual packageddevice.

[0023] The described lamination scheme allows virtually any number oflaminate matrices to be used to form a semiconductor package, with themaximum number being a function of the desired functionality,manufacturing cost and final package height.

[0024]FIG. 2 shows a cross-sectional view of integrated circuit 100where component set 6 consists of semiconductor dice 102 and 103 whichare housed in a package 101 that includes laminates 20 and 40 and asingulated encapsulant 108 of blanket encapsulant 8. Note the left andright surfaces of integrated circuit 100 being defined by cut lines 16and 26, respectively.

[0025] Laminate 20 is etched to form die flags 104-105 for mountingsemiconductor dice 102-103, respectively, and leads 106-107. Withcurrent processing technology, the minimum feature size of laminate 20,such as a spacing 109 between die flag 105 and lead 107, is about equalto its thickness. Hence, in one embodiment, where laminate 20 is twohundred fifty micrometers thick, the width of spacing 109 is also abouttwo hundred fifty micrometers.

[0026] Laminate 40 is attached at bottom surface 3 to top surface 5 oflaminate 20 as shown, with regions 206 and 207 electrically andmechanically connected to leads 106 and 107. Material is removed fromlaminate 40 in the region overlying die flags 104-105 so semiconductordice 102-103 can be mounted on laminate matrix 2 and further processedwithout damage. The thickness of laminate 40 is selected to be somewhatgreater than the thickness of semiconductor dice 102-103 so that topsurfaces 114-115 of semiconductor dice 102-103 are recessed below theplane of surface 22. For example, in an embodiment where semiconductordice 102-103 have a thickness of about two hundred fifty micrometers,the thickness of laminate 40 is selected to be about three hundredmicrometers.

[0027] A wire bond 111 is formed between semiconductor die 102 andregion 206 to make an external electrical connection from semiconductordie 102 through wire bond 111, region 206 and lead 106. Similarly, awire bond 112 is formed between semiconductor die 103 and region 207 formaking an external electrical connection from semiconductor die 103through wire bond 112, region 207 and lead 107. Electrical connection toexternal devices or a printed circuit board is made through featuresdefined on bottom surface 7, which remains exposed after theencapsulation process. A wire bond 113 is formed between semiconductordice 102 and 103 to provide a direct internal connection.

[0028] Surfaces 114-115 of semiconductor dice 102-103 lie in a planebelow surface 22, or nearly so. As a result, the loop height of wirebonds 111 and 112 is made significantly lower than would be possiblewith other semiconductor packaging techniques without introducingmechanical stresses in wire bonds 111-112. The short loop height reducesthe overall length of wire bonds 111-112, which provides a low parasiticinductance and resistance that improves the frequency response andoverall performance of integrated circuit 100. Moreover, since theheight of surface 22 is determined by the thickness of laminate 40,control over the loop height is improved and performance is moreconsistent.

[0029] Note that regions 206-207 are defined by cut lines 16 and 26,respectively, while leads 106-107 are recessed a distance from cut line16 and 26, respectively. In effect, the bottom surfaces of regions206-207 extend outwardly to form a shelf. This arrangement allowsencapsulating material to flow under and cover exposed portions ofregions 206-207 to form mold locks 120. Many semiconductor packages usemold locks to improve mechanical adhesion and prevent encapsulantlift-off to improve reliability. Because laminates are used to form moldlocks 120, their edges are substantially orthogonal, which produces ahigher mechanical and adhesive strength than what is achievable with thecurved surfaces of mold locks formed with a half-etching process.

[0030]FIG. 3 shows a cross-sectional view of integrated circuit 100 inan alternate embodiment as, for example, a transceiver in a wirelesscommunications device. The elements of integrated circuit 100 havestructures and functionality similar to what is shown and described inFIG. 2, except that package 101 is formed as a four-tiered laminationincluding laminates 20 and 40, a laminate 60 formed over laminate 40 anda laminate 80 formed over laminate 60 as shown. Semiconductor die 102 isconfigured as a high frequency, low noise amplifier while semiconductordie 103 is configured as a high frequency, high power transmittingstage. In one embodiment, semiconductor dice 102-103 are specified tooperate at a frequency greater than six gigahertz.

[0031] Regions 131-132 of laminate 40 function as leads of integratedcircuit 100. Regions 133-134 of laminate 40 and regions 135-136 oflaminate 60 are stacked as shown to function as spacers that support aregion 137 of laminate 80 at a height that avoids coming into electricalcontact with wire bond 112. Regions 131-137 are electrically coupledtogether to function as a Faraday cage or electromagnetic shield aroundsemiconductor die 103. Such shielding substantially blockselectromagnetic waves generated by semiconductor die 103 frompropagating to semiconductor die 102, or vice versa. As a result ofusing a lamination scheme to form package 101, semiconductor dice102-103 are shielded from each other. Moreover, electromagneticinterference is reduced, both internally and externally to package 101,while maintaining a low fabrication cost.

[0032]FIG. 4 shows an isometric view of integrated circuit 100 in yetanother embodiment, including a semiconductor package 101 formed withlaminates 20, 40 and 60 and encapsulant 108, and component set 6 thatcomprises semiconductor die 102, a packaged semiconductor device 320 andpassive components including an inductor 322 and a bypass capacitor 324.

[0033] Packaged semiconductor device 320 is implemented as anencapsulated, fully tested integrated circuit that is housed in package101 and re-encapsulated with encapsulant 108. Since there is no need touse a guide clamp or wire bonding tool, packaged semiconductor device320 can be disposed closer to semiconductor die 102 than could anotherbare die. Hence, in many cases such a “package-within-a-package” can beformed with a smaller size than what is needed to house two separateunpackaged semiconductor dice in the same package. Moreover, by finaltesting packaged semiconductor device 320 prior to housing in package101, the overall yield is improved and the fabrication cost is reduced.

[0034] Inductor 322 is electrically coupled between regions 151 and 153of laminate 60 as shown and to leads 161 and 164. Note that inductor 322is disposed laterally and crosses over leads 162 and 163, therebyproviding a flexible, low cost interconnection scheme. In oneembodiment, inductor 322 produces an inductance of about one microhenry.

[0035] Capacitor 324 is mounted vertically between different laminates,i.e., between die flag 104 of laminate 20 and region 155 of laminate 60.This use of laminates allows capacitor 324 to be physically locatedwithin package 101 adjacent to semiconductor die 102, where itsfiltering function is most effective because internally housedcomponents such as capacitor 324 have a lower parasitic inductance andresistance.

[0036]FIG. 5 is an isometric view of integrated circuit 100 in anotheralternate embodiment, including semiconductor package 101 formed withlaminates 20, 40 and 60, encapsulant 108 and semiconductor dice 102-103.

[0037] Semiconductor die 102 is formed with bonding regions 382 and 384and semiconductor die 103 is formed with a bonding region 383 for makingelectrical contacts. In one embodiment, bonding regions 382-384 areformed as bonding pads with a standard semiconductor interconnectmaterial such as aluminum or copper. In another embodiment, bondingregions 382-384 may include a built-up layer such as solder balls,plated copper or solder and the like.

[0038] To provide external electrical connections, laminate 60 is formedwith interconnect regions such as a laminate region 380 thatelectrically couples bonding region 382 to a lead 390, and a laminateregion 381 that electrically couples bonding regions 383-384 to a lead392. Electrical attachments are achieved using a standard thermalcompression or ultrasonic bonding process or a solder reflow process.Laminate 60 preferably is thin and therefore pliable enough tofacilitate bonding and to have a small feature size compatible withintegrated circuit bonding features. In one embodiment, laminate 60 isformed to a thickness of about fifty micrometers.

[0039] Note that laminate region provides not only a structure forelectrically coupling a semiconductor die to a package lead, but alsofor electrically coupling between semiconductor dice housed in the samepackage. Moreover, bonding with laminate regions 380-381 avoids the wireloops that are needed with standard wire bonds, which results in a lowparasitic inductance and a high operating frequency. In addition, highcurrents are easily accommodated by simply making high current laminateregions wide enough to reliably handle the high current, therebyavoiding the need for multiple bonding wires or even larger bondingwires. In fact, a small feature size can be combined with a high currentcapability and a low fabrication cost in the same structure by forminglaminate 60 with the appropriate feature sizes.

[0040]FIG. 6 is an exploded isometric view of semiconductor device orintegrated circuit 100 in still another alternate embodiment, includingsemiconductor package 101 formed with laminates 630 and 650, singulatedencapsulant 108 and semiconductor die 102.

[0041] In one embodiment, leadframe 620 includes laminate 630 andlaminate 650. Semiconductor die 102 is formed with bonding regions 382,384 and 670 for making electrical contacts. In one embodiment, bondingregions 382 and 384 are formed as bonding pads with a standardsemiconductor front side interconnect material such as aluminum orcopper, whereas bonding region 670 is formed as a bonding pad with astandard semiconductor backside metal such as titanium/nickel/silveralloy, titanium/nickel/gold alloy or the like.

[0042] To provide external electrical connections, laminate 650 isformed with interconnect regions such as a laminate region 6380 thatelectrically couples bonding region 382 to a lead 640, and a laminateregion 6381 that electrically couples bonding region 384 to lead 640. Inone embodiment, electrical attachment of laminate 650 to die 102 isperformed using standard fusion welding processes such as thermalcompression bonding or ultrasonic bonding. Fusion welds have thecharacteristic of providing a strong mechanical joint having excellentelectrical conductivity without introducing additional metals ormaterials into the weld. Thus, fusion welds have the advantage ofimproved electrical performance, such as less resistance, as a result ofhaving fewer dissimilar materials or metals. Fusion welds 6160 performedin regions 6170 and 6175 of laminate 650 fuse the material of thelaminate 650 to the material of the die 102 bonding regions 382 and 384respectively. Although shown as multiple fusion welds 6160, singlefusion welds per region may also be used where multiple welds are notrequired for cost, electrical/thermal performance, or mechanicalstrength.

[0043] Fusion welding the laminate 650 to the die 102 eliminates theneed to provide additional, expensive under bump metal (UBM) or othermetal deposits required in other electrical attachment methods. Forexample, a typical UBM scheme includes placing a barrier metal on top ofthe aluminum bond region, after which a second metal like titaniumtungsten is deposited, after which a seed metal is finally deposited topermit plating of the bump. Fusion welds are performed using equipmentthat recognizes the position of the die 102 with respect to the laminate650 and can thus adjust the location, number, and size of the fusionwelds 6160 to optimize the area of electrical attachment providingimproved electrical and thermal performance. In one embodiment,electrical attachments of laminate 650 to laminate 630 are achievedusing fusion welding of surface 6130 to surface 656 and surface 691 tosurface 655 respectively. In one embodiment, die 102 is attached tolaminate 630 using a standard thermal compression, ultrasonic bonding orsolder reflow process. In one embodiment, the solder reflow processincludes solder paste 150. Laminate 650 preferably is thin and thereforepliable enough to facilitate bonding and to have a small feature sizecompatible with integrated circuit bonding features. In one embodiment,laminate 650 is formed to a thickness of about fifty micrometers. Alsoshown is a solder ball 641 attached to lead 640 for attachment of theintegrated circuit 100 to a printed circuit board (not shown). Whilelead 640 is shown as rectangular, other shapes such as round, oblong,square, or the like are common.

[0044]FIG. 7 shows the electrical equivalent of the semiconductor deviceor integrated circuit of FIG. 6 showing the resistances attributable tothe dissimilar metals or materials in the various electricalconnections. For example, for an embodiment where die 102 is a powertransistor, the dissimilar metal or material junctions in the gate,source, and drain electrical paths are as follows. For the gate, a firstjunction 710 is formed between the region 382 of the die 102 and region6170 of laminate 650. A second junction 720 is formed between the lead640 and the solder ball 641. A third junction 730 is formed between thesolder ball 641 and the printed circuit board (not shown).

[0045] Similarly, the number of dissimilar metal or material junctionsin the source electrical path are as follows. A first junction 760 isformed between the region 384 of the die 102 and region 6175 of laminate650. A second junction 770 is formed between the lead 640 and the solderball 641. A third junction is formed between the solder ball 641 and theprinted circuit board (not shown).

[0046] The drain has four dissimilar junctions as follows. The die 102region 670 to paste 150 forms a first junction 740, paste 150 toleadframe 630 forms a second junction 750, leadframe 630 to solder ball641 forms a third junction 755, and a fourth junction 777 is formedbetween the solder ball to the printed circuit board (not shown).

[0047] Note, there is no dissimilar metal or material junction betweenlaminate 650 and 630 where mechanically and electrically joined usingfusing welding, thus there is no significant thermal or electricalresistance to degrade performance. Thus, in the case of the embodimentabove, the gate and source each have three dissimilar junctions, and thedrain has four. Reduced dissimilar junctions improve the operating speedof the device as well as decreasing power losses. Additionally, as thesource is on the top of die 102, heat is propagated away from theprinted circuit board rather than toward it.

[0048] In summary, the present invention provides a low costsemiconductor device or integrated circuit and package that economicallycombines small features with a high current capability. A leadframe formounting a semiconductor die is formed with a first laminate whosebottom surface is patterned with a lead of the integrated circuit. Asecond laminate has a bottom surface attached to a top surface of thefirst laminate to electrically couple the lead to the semiconductor die.The invention provides a low cost structure that combines a high leaddensity with a high current capability and provides higher quality leadlocks, crossover interconnections and electromagnetic shielding. Theneed for individual bonding wires is avoided by forming the secondlaminate in the desired bonding pattern, resulting in a higherperformance and lower cost than other structures.

What is claimed is:
 1. A method of making a semiconductor device,comprising: attaching a top surface of a first laminate to a bottomsurface of a second laminate to form a leadframe; and mounting a firstsemiconductor die to the leadframe to form the integrated circuit. 2.The method of claim 1, further comprising the step of encapsulating thefirst semiconductor die with a molding compound.
 3. The method of claim2, further comprising the step of removing material from the firstlaminate to form a mold lock with the molding compound.
 4. The method ofclaim 1, wherein the first and second laminates are formed with aconductive material.
 5. The method of claim 4, wherein the first andsecond laminates are each formed to a thickness greater than fiftymicrometers.
 6. A method of making a semiconductor device, comprising:mounting a first surface of a semiconductor die to a top surface of afirst laminate; and mounting a second laminate over the first laminateand to a second surface of the semiconductor die.
 7. The method of claim6, wherein the step of mounting the first surface includes the step ofelectrically coupling the first surface of the semiconductor die to afirst portion of the first laminate to form a first lead of theintegrated circuit and the step of mounting the second laminate includesthe step of electrically coupling a second surface of the semiconductordie to a second portion of the first laminate to form a second lead ofthe integrated circuit.
 8. The method of claim 6, wherein mounting thesecond laminate over the first laminate includes the step of fusionwelding or soldering.
 9. The method of claim 7, wherein mounting thesecond laminate to the first semiconductor die includes the step offusion welding.
 10. The method of claim 9, wherein the step of fusionwelding includes the step of making multiple fusion welds within aregion of the second laminate that is over a bond pad of thesemiconductor die.
 11. The method of claim 10, wherein the step ofmounting the semiconductor die on the top surface of the first laminateincludes the step of electrically attaching the semiconductor die to thefirst laminate with an electrically conductive mounting adhesive orsolder paste.
 12. The method of claim 7, further comprising the step ofcoating the first surface of the semiconductor die with solderablemetal.
 13. The method of claim 12, wherein the step of coating includesthe step of coating a first surface with titanium/nickel/silver alloy ortitanium/nickel/gold alloy.
 14. The method of claim 13, wherein thesecond surface of the semiconductor die includes aluminum.
 15. Themethod of claim 14 further comprising encapsulating the semiconductordie with a molding compound.
 16. The method of claim 15, furthercomprising the step of etching the first laminate to form a mold lockwith the molding compound.
 17. The method of claim 16, wherein thesecond laminate has a thickness greater than a thickness of thesemiconductor die.
 18. A method of electrically coupling a lead of aleadframe to a bonding pad of a semiconductor die comprising forming afusion weld on a laminate of the leadframe to fuse the lead to thebonding pad of the semiconductor die.
 19. The method of claim 18,wherein the bonding pad is formed of aluminum or aluminum alloy.
 20. Themethod of claim 18, wherein forming includes the steps of: forming thelead with the laminate; and forming a plurality of fusion welds on thelaminate for fusing the lead to the bonding pad of the semiconductordie.